Programmable logic devices (PLDs) are useful for a wide range of applications in which in-field programmability is desired. In addition, PLDs, such as field programmable gate arrays (FPGAs), provide a platform that facilitates reduced time to market with an extended product lifetime. FPGAs, however, have not been utilized to their full potential in certain power sensitive applications.
For example, while FPGAs are readily found in applications where operational power is plentiful, battery-powered applications tend towards implementations that utilize application specific integrated circuits (ASICs), since ASICs generally consume less power than FPGAs and may also incorporate power management features not generally found in FPGAs. Microprocessors and digital signal processors (DSPs) are also often selected for battery-powered applications, such as mobile communications, due in part to their ease of programmability and their extensive power management features. Power management features of processor based implementations, for example, can exhibit very low power consumption during inactive or standby periods.
Battery-powered applications, such as a mobile device in a mobile communications network, generally have two power modes: active power mode and standby power mode. Standby power mode is generally the predominant power mode, since a typical user application exhibits a very low duty cycle, whereby the mobile device is active for a short period of time, e.g., one hour, and inactive for a longer period of time, e.g., several hours to several days. As such, standby power mode, especially for battery-powered applications, tends to consume far less power than the active power mode, so as to extend the battery life of the mobile device.
Since FPGAs have conventionally been utilized for high-throughput processing applications with virtually unlimited energy supply, current FPGA architectures exhibit little or no power management capability. Accordingly, FPGA power consumption during the standby power mode may exceed the standby power consumption requirement for battery-powered applications by several orders of magnitude. FPGA power consumption is further exacerbated by the increase in leakage power due to downward scaling of transistor geometries in advanced semiconductor processing technologies.
Power gating transistors, also known as sleep transistors, have therefore been used to provide a gated connection from logic blocks within the FPGA to either the power supply node, or the reference supply node, or both, in order to reduce power consumption of the logic block when it is deactivated. In particular, if the logic block is active, then the power gating transistor is also activated, which provides a virtual ground connection, or a virtual power supply connection, or both, to the active logic block. If the logic block is inactive, on the other hand, then the power gating transistor is deactivated, which substantially eliminates any leakage current path that may exist from the deactivated logic block to either of the power supply node or reference supply node.
In such implementations, only the power gating transistor substantially contributes to the leakage current of the power gated logic block. By increasing the threshold voltage, Vt, of the power gating transistor, the leakage current may be further reduced. Power gating transistors, however, have conventionally been placed within the logic core of the FPGA. Thus, further reduction of the leakage current in the power gating transistors is substantially limited by the advancing processing technologies. Alternative power gating structures, therefore, continue to be developed, so that FPGAs may be increasingly utilized in low power consumption applications, even when the logic core device geometries of the FPGAs are reduced.